1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly to a structure of a novel capacitor suited for an analog circuit and to a novel manufacturing method of the same.
2. Description of Related Art
It is desirable to use a device whose bias dependency (gate bias) is small for a capacitor used in an analog circuit because it is required to operate at high speed.
FIG. 1 is a sectional view of part of a known semiconductor integrated circuit device used for an analog circuit, in which a MOS type field effect transistor (hereinafter referred to as a MOS transistor) and a two-layered poly-capacitor are formed. A field oxide film 102, i.e. a device separating region, made of LOCOS or the like is formed on the surface region of a semiconductor substrate 120 made of a P-type silicon or the like. In this known device, an N-type well region (N well) 101 is formed in the semiconductor substrate 120, a P-type MOS transistor (PMOS transistor) is formed on the device region of the N well 101 and a MOS capacitor is formed on the field oxide film 102 in the N well 101. A P+ source/drain region 117 of the two-layered poly-transistor is formed in a device region surrounded by the field oxide film 102. A gate oxide film 108 is formed on the part between the P+ source/drain regions 117 by means of thermal oxidation, for example. A gate electrode is formed on the gate oxide film 108.
The gate electrode is composed of a first poly-silicon film 109 directly formed on the gate oxide film 108, a third poly-silicon film 114 formed on the first poly-silicon film 109, and a tungsten silicide film 115 formed on the third poly-silicon film 114. Meanwhile, a first electrode 119, made of a poly-silicon film, of the capacitor is formed on the field oxide film 102. Then, a silicon oxide film 121 which becomes a dielectric film is formed on the first electrode 119. A second electrode is formed on the silicon oxide film 121. The second electrode is composed of a second poly-silicon film 112 directly formed on the silicon oxide film 121, another third poly-silicon film 114 formed on the second poly-silicon film 112 and another tungsten silicide film 115 formed on the third poly-silicon film 114. A BPSG (Boron-doped Phospho-Silicate Glass) film 118 for example is coated on the semiconductor substrate 120 so as to protect the two-layered poly-capacitor and the MOS transistor. The surface of the BPSG film 118 is flattened by means of CMP (Chemical Mechanical Polishing), for example. A metal wire 122 on film is coated further on the semiconductor substrate, thus completing the semiconductor chip.
In the semiconductor integrated circuit, the voltage coefficient of the capacitor using the semiconductor substrate such as silicon as one electrode thereof is decided by a thickness of an insulating film between the capacitor electrode and the substrate and concentration of impurity implanted to the surface of the silicon substrate. The voltage coefficient degrades when the thickness is thinned and when the concentration is lowered. However, with the increase and further micronization of the integration of LSIs, it is required to thin the thickness of the gate oxide film of the MOS transistor in order to suppress a short channel effect. In the capacitor using the oxide film having the same thickness with the gate oxide film of the MOS transistor as the insulating film, the impurity concentration of the semiconductor substrate cannot exceed a solid solubility limit of the impurity within silicon and the insulation of the oxide film formed thereon also degrades when the concentration is too high, so that it is necessary to suppress the concentration to a certain degree. In such case, when positive or negative voltage is applied to the capacitor electrode, a depletion layer is formed on the silicon substrate side and the substantial thickness of the oxide film fluctuates due to the fluctuation of the applied voltage, thereby increasing the coefficient of voltage of the capacitance.
On the other hand, although an electrode such as a poly-silicon film different from the gate electrode may be used, for example, for the lower electrode of the capacitor in order to minimize the coefficient of voltage, the height of the capacitor forming region is thickened as compared to the gate electrode forming region by the thickness of the lower poly-silicon film as shown in FIG. 1 as a result. Further, it is essential to use a polishing process such as the CMP method as described above which does not involve heat treatment as the flattening technology in order to advance the micronization in the future. However, there arises a problem in such case that the upper electrode part of the capacitor, whose stepped structure differs, is exposed on the surface and the insulation with the upper aluminum wiring layer cannot be maintained as shown in FIG. 1.